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| PRELIMINARY SemiWell Semiconductor SFD60N03L Logic N-Channel MOSFET Features Low RDS(on) (0.019 )@VGS=10V Low Gate Charge (Typical 21.5nC) Low Crss (Typical 130pF) Improved dv/dt Capability 100% Avalanche Tested Maximum Junction Temperature Range (150C) Symbol 2. Drain 1. Gate 3. Source General Description This Power MOSFET is produced using SemiWell's advanced planar stripe, DMOS technology. This latest technology has been especially designed to minimize on-state resistance, have a low gate charge with superior switching performance and rugged avalanche characteristics. This Power MOSFET is well suited for synchronous DC-DC Converters and Power Management in portable and battery operated products. D-PACK (TO-252) 2 1 3 Absolute Maximum Ratings Symbol VDSS ID IDM VGS EAS dv/dt PD TSTG, TJ TL Drain to Source Voltage Continuous Drain Current(@TC = 25C) Continuous Drain Current(@TC = 100C) Drain Current Pulsed Gate to Source Voltage Single Pulsed Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation(@TA = 25 C) Total Power Dissipation(@TC = 25 C) Derating Factor above 25 C Operating Junction Temperature & Storage Temperature Maximum Lead Temperature for soldering purpose, 1/8 from Case for 5 seconds. (Note 2) (Note 3) (Note 1) Parameter Value 30 40.3 25.5 161 Units V A A A V mJ V/ns W W W/C C C 20 270 7.0 2.5 56 0.45 - 55 ~ 150 300 Thermal Characteristics Symbol RJC RJA RJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient * Thermal Resistance, Junction-to-Ambient Value Min. - Typ. - Max. 2.25 50 110 Units C/W C/W C/W * When mounted on the minimum pad size recommended (PCB Mount) September, 2002. Rev. 0. Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. 1/7 SFD60N03L Electrical Characteristics Symbol Off Characteristics BVDSS BVDSS/ TJ IDSS Drain-Source Breakdown Voltage VGS = 0V, ID = 250uA 30 0.02 1 10 100 -100 V V/C uA uA nA nA ( TC = 25 C unless otherwise noted ) Parameter Test Conditions Min Typ Max Units Breakdown Voltage Temperature coefID = 250uA, referenced to 25 C ficient Drain-Source Leakage Current Gate-Source Leakage, Forward Gate-Source Leakage, Reverse VDS = 30V, VGS = 0V VDS = 24V, TC = 125 C VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VDS = VGS, ID = 250uA VGS = 10 V, ID = 20.2A VGS = 5 V, ID = 20.2A IGSS On Characteristics VGS(th) RDS(ON) Gate Threshold Voltage Static Drain-Source On-state Resistance 1.0 0.013 0.017 3.0 0.019 0.024 V Dynamic Characteristics Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance VGS =0 V, VDS =25V, f = 1MHz 1010 450 130 1320 585 170 pF Dynamic Characteristics Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge(Miller Charge) VDS =24V, VGS =5V, ID =60A see fig. 12. (Note 4, 5) VDD =15V, ID =30A, RG =50 see fig. 13. (Note 4, 5) 20 55 50 75 21.5 3.6 10.7 50 120 110 160 28 nC ns - Source-Drain Diode Ratings and Characteristics Symbol IS ISM VSD trr Qrr Parameter Continuous Source Current Pulsed Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Test Conditions Integral Reverse p-n Junction Diode in the MOSFET IS =40.3A, VGS =0V IS=60A,VGS=0V,dIF/dt=100A/us Min. - Typ. 40 35 Max. 40.3 161 1.5 - Unit. A V ns nC NOTES 1. Repeativity rating : pulse width limited by junction temperature 2. L = 165uH, IAS =40.3A, VDD = 15V, RG = 0 , Starting TJ = 25C 3. ISD 60A, di/dt 300A/us, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse Width 300us, Duty Cycle 2% 5. Essentially independent of operating temperature. 2/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFD60N03L Fig 1. On-State Characteristics VGS 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Top : Fig 2. Transfer Characteristics 10 2 10 2 ID, Drain Current [A] ID, Drain Current [A] 10 1 150 C 25 C -55 C o o o 10 1 Notes : 1. 250 s Pulse Test 2. TC = 25 -1 0 1 Notes : 1. VDS = 15V 2. 250 s Pulse Test 10 10 10 10 0 0 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V] Fig 3. On Resistance Variation vs. Drain Current and Gate Voltage 50 Fig 4. On State Current vs. Allowable Case Temperature 10 2 RDS(ON), Drain-Source On-Resistance [m ] VGS = 5V 30 VGS = 10V 20 IDR, Reverse Drain Current [A] 40 10 1 10 Note : TJ = 25 150 25 Notes : 1. VGS = 0V 2. 250 s Pulse Test 0 0 40 80 120 160 200 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ID, Drain Current [A] VSD, Source-Drain voltage [V] Fig 5. Capacitance Characteristics 3000 Ciss=Cgs+Cgd(Cds=shorted) Coss=Cds+Cgd Crss=Cgd Fig 6. Gate Charge Characteristics 12 VGS, Gate-Source Voltage [V] 2500 10 VDS = 15V VDS = 24V Capacitance [pF] 2000 Notes : 1. VGS = 0V 2. f=1MHz 8 1500 6 Ciss 1000 4 Coss 500 2 Note : ID = 60.0 A Crss 0 0 5 10 15 20 25 30 35 0 0 5 10 15 20 25 30 35 40 45 VDS, Drain-Source Voltage [V] Qg, Total Gate Charge [nC] 3/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFD60N03L Fig 7. Breakdown Voltage Variation vs. Junction Temperature 1.2 2.5 Fig 8. On-Resistance Variation vs. Junction Temperature BVDSS, (Normalized) Drain-Source Breakdown Voltage RDS(ON), (Normalized) Drain-Source On-Resistance 1.1 2.0 1.5 1.0 1.0 0.9 Notes : 1. VGS = 0 V 2. ID = 250 A 0.5 Notes : 1. VGS = 10 V 2. ID = 24 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Fig 9. Maximum Safe Operating Area 50 Operation in This Area is Limited by R DS(on) Fig 10. Maximum Drain Current vs. Case Temperature 40 ID, Drain Current [A] 10 100 s 1 ms 10 ms DC ID, Drain Current [A] 2 30 20 10 1 Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o o 10 10 -1 10 0 10 0 10 1 10 2 0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TC, Case Temperature [] Fig 11. Transient Thermal Response Curve Z JC Thermal Response (t), 10 0 D = 0 .5 0 .2 0 .1 0 .0 5 N o te s : 1 . Z J C = 2 .2 5 /W M a x . (t) 2 . D u ty F a c to r, D = t 1 /t 2 3 . T JM - T C = P D M * Z JC (t) 10 -1 0 .0 2 0 .0 1 s in g le p u ls e 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] 4/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFD60N03L Fig. 12. Gate Charge Test Circuit & Waveforms 50K 12V 200nF 300nF Same Type as DUT VDS VGS Qg 5V Qgs Qgd VGS DUT 1mA Charge Fig 13. Switching Time Test Circuit & Waveforms VDS RL VDD ( 0.5 rated V DS ) VDS 90% 5V Pulse Generator RG DUT Vin 10% td(on) t on tr td(off) t off tf Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms VDS ID RG L VDD BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD BVDSS IAS ID (t) 10V DUT VDD tp VDS (t) Time 5/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFD60N03L Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ IS L Driver RG Same Type as DUT VDD VGS * dv/dt controlled by RG * IS controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current IS ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt Vf VDD Body Diode Forward Voltage Drop 6/7 Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. SFD60N03L TO-252(D-PAK) Package Dimension Dim. A B C D E F G H I J K L mm Min. 6.48 5.0 7.42 2.184 0.762 1.016 Typ. 6.604 5.08 7.8 2.286 0.813 1.067 2.286 2.286 0.534 1.016 0.61 1.067 0.508 0.762 1.57 0.686 1.118 0.021 0.04 Max. 6.73 5.21 8.18 2.388 0.864 1.118 Min. 0.255 0.197 0.292 0.086 0.03 0.04 Inch Typ. 0.26 0.2 0.307 0.09 0.032 0.042 0.09 0.09 0.024 0.042 0.02 0.03 0.06 0.027 0.044 Max. 0.265 0.205 0.322 0.094 0.034 0.044 A B D E C I 2 1 G 3 H J F K L 1. Gate 2. Drain 3. Source 7/7 |
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